CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors

Provided by: edaa
Topic: Hardware
Format: PDF
Soft error has been identified as one of the major challenges to CMOS technology based computing systems. To mitigate this problem, error recovery is a key component, which usually accounts for a substantial cost, since they must introduce redundancies in either time or space. Consequently, using state-of-art recovery techniques could heavily worsen the design constraint, which is fairly stringent for embedded system design. In this paper, the authors propose a HW/SW methodology that generates the processor, which performs finely configured error recovery functionality targeting the given design constraints.

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