Current Starved Voltage Controlled Oscillator for PLL Using 0.18um CMOS Process
A five stage current starved Voltage Controlled Oscillator (CMOS VCO) is designed in this paper. The design is implemented in Tanner environment with high oscillation frequency and low power consumption. Oscillation frequency of the designed VCO ranges from 25.70MHz to 222.53MHz. The circuit is simulated using 180nm SCN018 technology. Simulation results reported that the power consumption is 58.47uA at 1.8V VDD. Design procedures and simulation results are illustrated. This design is suitable for PLL as a frequency multiplier.