Institute of Electrical & Electronic Engineers
Concurrent testing of the cores in a core-based System-on-Chip (SoC) reduces the test application time but increases the test power consumption. Power models, test architecture design, and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is simple for a scheduling algorithm to handle but is pessimistic. In this paper, the authors propose a cycle-accurate power model with a power value per clock cycle and a corresponding test architecture design and scheduling algorithm.