Cycle-Approximate Retargetable Performance Estimation at the Transaction Level

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Provided by: edaa
Topic: Hardware
Format: PDF
In this paper the authors present a novel cycle-approximate performance estimation technique for automatically generated Transaction Level Models (TLMs) for heterogeneous multicore designs. The inputs are application C processes and their mapping to processing units in the platform. The processing unit model consists of pipelined data-path, memory hierarchy and branch delay model. Using the processing unit model, the basic blocks in the C processes are analyzed and annotated with estimated delays. This is followed by a code generation phase where delay-annotated C code is generated and linked with a SystemC wrapper consisting of inter-process communication channels.
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