Cycle-Count-Accurate Processor Modeling for Fast and Accurate System-Level Simulation

Provided by: edaa
Topic: Hardware
Format: PDF
Ideally, system-level simulation should provide a high simulation speed with sufficient timing details for both functional verification and performance evaluation. However, existing Cycle-Accurate (CA) and Cycle-approXimate (CX) processor models either incur low simulation speeds due to excessive timing details or low accuracy due to simplified timing models. To achieve high simulation speeds while maintaining timing accuracy of the system simulation, the authors propose a first Cycle-Count-Accurate (CCA) processor modeling approach which pre-abstracts internal pipeline and cache into models with accurate cycle count information and guarantees accurate timing and functional behaviors on processor interface.

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