Provided by: Creative Commons
Date Added: Jul 2013
In this paper, by operating the shifting and addition in parallel, an Error-Compensated Adder-Tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput Discrete Cosine Transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this paper so as to meet Peak-Signal-to-Noise-Ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous papers.