Institute of Electrical & Electronic Engineers
Main memory performance is becoming an increasingly important factor contributing to overall system performance, especially due to the so-called memory wall. The Hybrid Memory Cube (HMC) is an attempt to overcome this memory wall by stacking DRAM on top of a logic die and interconnecting them with dense and fast Through Silicon Vias (TSVs). However, modeling the Hybrid Memory Cube (HMC) in HotSpot has indicated that this cube has a natural temperature variation, with the hottest layers at the bottom and the cooler layers at the top. High temperatures and variations within a DRAM can result in reduced performance and efficiency, especially when Dynamic Thermal Management (DTM) schemes are used to throttle DRAM bandwidth whenever temperature gets too high.