Data Encoding Techniques for Low Power Address and Data Buses
As technology shrinks, the power dissipated by the links of a Network-on-Chip (NoC) starts to compete with the power dissipated by the other elements of the communication subsystem, namely, the routers and the Network Interfaces (NIs). In this paper, the authors present a set of data encoding schemes aimed at reducing the power dissipated by the links of a NoC. The proposed schemes are general and transparent with respect to the underlying NoC fabric (i.e., their application does not require any modification of the routers and link architecture).The proposed encoder will be coded in HDL and simulated using Xilinx 12.1.
Provided by: International Journals of Advanced Information Science and Technology (IJAIST) Topic: Security Date Added: Jun 2015 Format: PDF