Data Placement in HPC Architectures with Heterogeneous Off-Chip Memory

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Storage
Format: PDF
The performance of HPC applications is often bounded by the underlying memory system's performance. The trend of increasing the number of cores on a chip imposes even higher memory bandwidth and capacity requirements. The limitations of traditional memory technologies are pushing research in the direction of hybrid memory systems that, besides DRAM, include one or more modules based on some of the higher density non-volatile memory technologies, where one of them will provide the required bandwidth, while the other will provide the required capacity for the application.
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