University of Pécs
Contemporary FPGA-based reconfigurable systems have been widely used to implement computation-intensive applications. In these applications data transfer and storage consume a large part of the system energy. Exploiting data reuse can introduce significant power savings, but also introduces extra requirement for on-chip memory. To aid data reuse design exploration, the authors present a optimization approach to achieve a power-optimal design satisfying area constraints in a targeted reconfigurable platform. The data reuse exploration problem is mathematically formulated and shown to be equivalent to a Multiple-Choice Knapsack problem.