To obtain the benefit of aggressive CMOS scaling, Chip Multi-Processors (CMP) has a tendency of integrating more processors on one chip. The increase of cores and voltage factors are increasing susceptibility of CMP to transient faults. To solve this problem, a lot of methods are proposed to enhance the fault tolerance ability of CMP. In these methods, coarse-grain Thread-Level Redundancy (TLR) is more attractive because tolerating long verification latencies is supported. However, the authors observe that an external write operation not only results in memory inconsistency, but also induces redundancy coherence conflict.