Reversible circuit design is an attractive research study that has applications in quantum computing, low power design and cryptography. In other side, two of the most important circuits in arithmetic units are multipliers and multi-operand addition circuits. Conventional multiplier has three main stages which partial product reduction stage has an impressive impact in the total delay of the circuit. This paper is a multi-operand addition that reduces the number of partial products. Half adders and full adders are the main arithmetic components that are used in the reduction stage of multipliers.