In this paper, the authors propose a reversible 4-Bit binary counter with parallel load. It has minimum complexity and quantum cost considerably. The planned circuit is the first attempt of designing a 4-Bit binary counter with parallel load. Counter is basically a register that goes through a predetermined sequence of state. The reversible gates in the counter are connected in such a way as to produce the prescribed sequence of binary states. Then this counter receives a 4-Bit data from input and delivers data to D flip flop in subsequently cycle. Loading data from input is determined with load property.