Design a 5T SRAM by Using Self Controllable Voltage Level Leakage Reduction Technique with CMOS Technology

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Provided by: International Association of Scientific Innovation and Research (IASIR)
Topic: Hardware
Format: PDF
The combination of complexity and speed, most of the application in VLSI system. The integrated circuit memories are essential elements for digital and analog circuit. High performance and cost effective circuits implement by using a CMOS Technology. Here the authors implemented a 5T SRAM (Static Random Access Memory) by using a Self-controllable Voltage Level (SVL) technique. The SVL technique is low leakage power reduction technique in which has upper SVL and lower SVL is used. The simulation is done by using a MICROWIND 3.1 and DSCH2 with SVL technique.
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