Design a Low Power Built in Self-Test (BIST) Architecture for Fast Multiplier and Optimize in Terms of Real Time Functionality

Provided by: Auricle Technologies
Topic: Hardware
Format: PDF
Aiming low power during testing, may present a methodology for deriving BIST architecture for fast multipliers. In the author propose research several design rules for designing the Wallace tree in order to be fully testable under the cell fault model. The proposed low power BIST Architecture for the derived multipliers are achieved by: introducing test pattern generators, properly assigning the TPGs outputs to the multiplier inputs and significantly reducing the test vector length. In this paper, the author has implemented 4bit multiplier with many Test Pattern Generators (TPGs) alternative.

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