Provided by: International Journal of Electronics and Electrical Engineering (IJEEE)
The basic building block of any computational circuit is adder which affects the performance of the system so there is a need for an adder with low power dissipation and small area. In this paper, a high performance and low power dissipation full adder cell is designed using Shannon theorem. The hardware includes a four bit 2's compliment adder/subtractor using proposed full adder. The adder is optimized using transistor sizing technique. Simulations were performed using microwind 3.1 VLSI CAD tool and schematic is generated by using DSCH 3.1 CAD tool.