International Journal of Engineering and Advanced Technology (IJEAT)
In this paper, the authors have studied microcomputer without interlocked pipeline stages instruction format instruction data path decoder module function and design theory based on RISC CPUT instruction set. They have also designed Instruction Fetch (IF) module of 32-bit CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module address arithmetic module check validity of instruction module synchronous control module. Function of IF modules are implemented by pipeline and simulated successfully on Xilinx Spartan 3E FPGA device..