Provided by: Institute of Electrical and Electronics Engineers
Date Added: Sep 2013
In this paper, the authors describe the architecture, design, analysis and simulation and measurement results of the 3D-MAPS (3D Massively pArallel Processor with Stacked memory) chip built with a 1.5V, 130nm process technology and a two-tier 3D stacking technology using 1.2um-diameter, 6um-height Through-Silicon-Vias (TSVs) and 3.4um-diameter face-to-face bond pads. 3D-MAPS consist of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers.