International Journal of Computer and Electrical Engineering (IJCEE)
Multi-valued logic synthesis is a very promising and affluent research area at present because of allowing designers to build much more efficient computers than the existing classical ones. In this regard, research on ternary logic synthesis has got impetus in the recent years. Many existing literature are mainly perceptive to the realization of efficient ternary reversible processors. This paper is based on the design of a reversible systolic array, one of the best examples of the parallel processing, using micro level ternary Toffoli gate. General architecture of the ternary reversible systolic array multiplier is shown along with example.