Design and Analysis of a Conventional Wallace Multiplier in 180nm CMOS Technology
Multiplier is an important building block in much electronic system design. There are many available methods and techniques for designing multipliers. Wallace multiplier is important and popular multiplier architecture. In this paper, design and analysis of a conventional Wallace multiplier is presented by using Cadence virtuoso in 180nm CMOS technology. Performance analysis in terms of power, delay, and power delay product are performed for a 4-bit Wallace multiplier in 180nm CMOS technology. The power and delay of the designed multiplier are 689.3µW and 50µs respectively.