Provided by: International Journal of Innovative Technology and Exploring Engineering (IJITEE)
Date Added: Apr 2013
In this paper, the authors design a low power high speed sense amplifier for CMOS SRAM. It has to sense the lowest possible signal swing from the SRAM bit lines and its response time should be very fast while keeping the power consumption within a tolerable limit. in this presented sense amplifier will be based on latest architectures available in literature and they focus will be to improve the power consumption and response time of this sense amplifier. Typical memory that is available has read access time of 12 ns and power consumption of 160mW and supply voltage ranges from 1.8 to 3.3V and rise time SAEN signal ranges from 100 to 400ps and offset voltages ranges from 45 to 80mv.