As the density and operating speed of CMOS VLSI chips increases, leakage power dissipation becomes more and more significant. This paper presents a leakage power behavior in pulse triggered flip-flop. All the designs are simulated with and without the application of leakage reduction techniques and the readings are presented. By analyzing the leakage path of flip flops the authors propose a method to reduce the leakage power of flip flops in this paper. The circuit is simulated using tanner tool spice simulator. The result at a frequency of 400MHz shows that proposed flip-flop consume less power.