Design and Analysis of Gate-Stack Doping-Less Tunnel Field Effect Transistor

Provided by: International Journal of Pure and Applied Research in Engineering and Technology (IJPRET)
Topic: Hardware
Format: PDF
In this paper, the authors propose a gate-stack doping-less tunnel field effect transistor is proposed using a double-gate Doping-Less TFET (DLTFET) with a multi-layer gate-stack architecture. The device characteristics are demonstrated and compared with DLTFET. It is found that the proposed architecture is having better performance than DLTFET. It is based on charge plasma concept. There is no source and drain doping applied. Thus, it is free from random dopant fluctuation issue and highly reliable. The gate dielectrics are used in stack manner to form a multi-layer architecture.

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