Design and Analysis of High Performance Double Edge Triggered D-Flip Flop Based Shift Registers
In this paper, the authors enumerate the efficient design and analysis of Serial-In-Serial-Out (SISO), Serial-In-Parallel-Out (SIPO), Parallel-In-Serial-Out (PISO) and Parallel-In-Parallel-Out (PIPO) shift registers using low power Double Edge Triggered D Flip-Flop (DETFF). DETFF are bi-stable flip-flop circuits in which data is latched at rising and falling edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock frequency. Therefore, power consumption in DETFF based circuits can be reduced.