Design and Analysis of Low Power 1-Bit Full Adder at 45 nm CMOS Technology
In this paper, the authors propose a new optimized low power CMOS 1-bit full adder at 45nm technology. The design and simulation of a conventional CMOS 1-bit full adder and the proposed design has been presented. This paper shows comparison about post layout simulations of designed low power CMOS full adder, it also explains about performance analysis of optimized low power CMOS full adder at different loads. The proposed design has achieved 63.11nW active power consumption with propagation delay of 0.254ns and having leakage current of 0.798nA at the supply voltage of 0.7V.