Design and Analysis of Low Power Pulse Triggered FlipFlop Based on Single Feed-Through Scheme

In this paper, a low-power Flip-Flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type Pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design Data-Close-to-Output (ep-DCO) by 8.2% in data-to-Q delay.

Provided by: International Journal of Engineering Research (IJER) Topic: Hardware Date Added: Mar 2014 Format: PDF

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