Design and Analysis of Low Power Single Edge Triggered D Flip Flop Based Shift Registers

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Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Topic: Hardware
Format: PDF
In this paper, analysis of average power, delay and power delay product is done for various shift registers (SISO, SIPO, PISO and PIPO) low power flip-flops are crucial for the design of low-power digital systems. As Metal-Oxide Semi-conductor Field Effect Transistor (MOSFET) devices are scaled down to nanometer ranges, Complementary MOS (CMOS) circuit's total power consumption has a new definition. Due to integration of millions of components and shrinking process technology, now-a-days leakage power tends to play a major role in total power consumption.
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