Design and Analysis of Low-Power Subtractor Circuits using P-XOR Logic Gates with Sleep Approach

Provided by: International Journal of Advanced Research in Computer Engineering & Technology
Topic: Hardware
Format: PDF
In this paper, the authors have presented the design of a low-power full subtractor circuit using P-XOR/G-XNOR pass transistors logic gates. The main aim of designing the low power full subtractor circuit is the increasing circuit's complexity and demand of portable devices. Full subtractor circuit is one of the main components of most of the arithmetic and logic circuits. Full subtractor circuit is implemented using one or more XOR/XNOR gates which consume the large part of the energy.

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