Design and Analysis of SRAM Cell for Reducing Leakage in Submicron Technologies Using Cadence Tool

Provided by: Iosrjournals
Topic: Hardware
Format: PDF
Leakage power has become a great challenge now-a-days. As the size of the device shrink the leakage power increases. So, the leakage power is the very serious problem in CMOS chips. As the authors move towards the sub-micron technology, the device consistency and the threshold voltage become smaller. When decreasing the supply voltage, the threshold voltage and the oxide thickness decreases due to this leakage increases. This paper is to reduce the leakage of the SRAM.

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