In modern digital systems large capacity and data transfer rate is required. Synchronous DRAM (SDRAM) becomes the memory of choice due to its speed, burst access and pipeline features. A controller is required to provide proper commands for SDRAM initialization, read/write accesses and memory refresh. This paper describes the design of a synthesizable SDRAM controller IP core which is vendor neutral. The design is described using Verilog HDL, simulated using ModelSim and prototyped in Altera platform FPGA. Resource utilization and power analysis was done using Altera Quartus II. Hardware test results are obtained from signal tap logic analyzer.