Design and Comparative Analysis of Conventional Adder and Pipelined Adder
Adding two binary numbers is a basic operation in binary electronic processing system. Pipelining digital systems has been shown to provide significant performance gains over non-pipelined systems and remains a standard in microprocessor design. The desire for increased performance has seen a push for pipelines. Pipelining is considered to be a good technique for increasing the circuit speed. In this paper, 4-bit conventional adder and 4-bit pipelined adder has been implemented using Cadence virtuoso tool and simulation was performed using the generic 0.18 Î¼m CMOS Technology at 5V.