Design and Evaluation of Hysteresial Threshold Gate Based on Neuron MOS

Provided by: NORTH ATLANTIC UNIVERSITY UNION
Topic: Hardware
Format: PDF
High-Speed and high-performance synchronous circuit design in VLSI suffer some serious problems such as clock skew, clock noise and larger power dissipation. In this paper, threshold gates with hysteresis using Neuron MOS (νMOS) are presented as basic elements in Null Convention Logic (NCL) circuits. NCL, which proposed by the researchers, needs special gates having hysteresis, because NCL uses different ternary logic systems in computation phase and wiping phase of asynchronous behavior, respectively. To implement the dynamic behavior, the traditional NCL circuits exploit extended CMOS structure which consists of a number of cascaded and parallel transistors connections.

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