Design and FPGA Implementation of 100Gbit/s Scrambler Architectures for OTN Protocol
In this paper, the authors describe design and FPGA (Field Programmable Gate Array) implementation of two scrambler architectures, with applications in 100Gbit/s Optical Transport Network (OTN) systems. And comparing these two scrambler architectures using some parameters like resource utilization and performance. The scrambler architectures are modeled using Verilog HDL to verify the correct operation. The programmable logic synthesis and simulation were performed using the tools provided by Xilinx Inc. (ISE 13.4 and Modelsim6.3c) with a Virtex-6 as target device.