Design and FPGA Implementation of High Speed 128x 128 Bits Vedic Multiplier Using Carry Look-Ahead Adder

In this paper, describes about the design of 128-bit Vedic multiplier using ancient Vedic mathematics. The proposed multiplier is designed to take two 128-bit inputs, and prescribed each 128-bit input into two 64-bit blocks this can be used to reduce the complication of the design equating to the other multiplication technique used in digital signal processing and cryptographic algorithm Urdhva Tiryagbhyam technique is used on these blocks and arranges the partial products in a way so they can be added using carry look-ahead adder and equated with ripple carry adder. The proposed architecture minimizes the combinational delay which makes more efficient than the ripple carry adder.

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