International Society of Thesis Publication (ISTP)
In this paper, the authors present the design and FPGA implementation of sequential digital 9-tap FIR filter using a novel micro programmed controller based design approach. In the paper, the FIR filter is designed for operation controls by micro programmed controller. The proposed FIR filter is coded in VHDL using modular design approach, and implemented in Spartan-3E FPGA. The performance evaluation and synthesis results obtained through Xilinx ISE 14.2 synthesis tool and functionally checked in Model sim 10.1 student edition.