Design and Hardware Implementation of 128-Bit Vedic Multiplier
In this paper, multiplier architecture is proposed based on algorithm of ancient Indian Vedic mathematics, high speed applications. It is based on the vertical and crosswise algorithm of ancient Indian Vedic Mathematics, Urdhva Tiryakbhyam Sutra generating all partial products and their sums in one step. The design basic block which are adders are designed in a generic way so N-bit multiplier design can be done using the designed architecture. The design implementation is done using VHDL. The design code is tested using Modelsim-Altera 10.1b simulator.