Design and Implemenation of High Speed 64- Bit Multiply and Accumulator Unit Using FPGA
In this paper, the authors proposed a design of high speed MAC unit based on Vedic multiplier algorithm. Generally MAC useful application such as digital signal processing like FFT (Fast Fourier Transform) transforms convolution and correlation. MAC is hardware based module therefore first design of multiplier block and second one is adder block. In this paper, to implementation 64bit MAC with reduces the delay and increase the speed of system. The coding done by Verilog-HDL and its synthesis and simulation on XILINX ISE.14.5 tool.