Design and Implement of Traffic Filtering System Based on FPGA

Provided by: AICIT
Topic: Hardware
Format: PDF
In order to identify and filter new application's traffic in 100M-Ethernet network in real-time, a traffic filtering system based on FPGA is given in this paper. An optimized k-means algorithm is integrated to identify the traffic. Traffic identifying and filtering IP core is designed and further realized combining the SoC technique on XC6SLX45-2 chip. The authors also consider the advantages of bitwise operation in hardware, i.e., the implemented of address map module, these operation runs more effectively with hardware mode.

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