Design and Implementation of 32-Bit Vedic Multiplier on FPGA
In this paper, the authors describe the design and FPGA implementation of 32-bit Vedic multiplier. The proposed multiplier is designed to take two 32-bit inputs, and arranged each 32-bit input into two 16-bit blocks apply vertically and crosswise method on these blocks and arranges the partial products in a manner so they can be added using one carry save adder. The proposed architecture minimizes the combinational path delay which makes it more efficient. Simulation is done on ModelSim 5.7 simulator using Verilog HDL. Implementation is done on Spartan 3E FPGA, XC3S500 (device), FG320 (package) and -5 (grade speed).