Design and Implementation of 4-Bit Flash ADC Using Folding Technique in Cadence Tool
The trend toward increased integration of analog and digital circuitry requires that data converters be embedded in large digital ICs. Mixed-signal applications such as Partial Response Maximum-Likelihood (PRML) read channels and Gigabit Ethernet require high-speed low-resolution ADCs which are usually implemented with the flash architecture. In this paper, the authors design a pipelined flash Analog-to-Digital Converter (ADC) to achieve high speed using 0.18um CMOS technology. The results obtained are also presented here. The physical circuit is more compact than the previous design. Power, processing time, and area are all minimized. This design can be used for modem high speed ADC applications.