Design and Implementation of 64 Bit Multiplier by Using Carry Save Adder
In this paper, the authors have shown the design and implementation of 64 bit multiplier by using multi bit flip flop shift register and carry save adder. In arithmetic operations addition and multiplication are having a major role. When the number of bits increases, the complexity of adder circuits increases and speed performance decreases. Their proposed system uses two 64 bit numbers and multiplies to form a 128 bit number, which is for larger applications. Proposed carry save adder based multiplier, on comparing with the carry look ahead adder based 64 bit multiplier, the results showing time (speed) decreased by 93.5% approximately and when comparing with the carry select adder based 64 bit multiplier-time (speed) decreased up to 88%.