Design and Implementation of a High Speed 64 Bit Kogge-Stone Adder Using Verilog HDL

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Provided by: International Journal of Electrical and Electronic Engineering & Telecommunications (IJEETC)
Topic: Hardware
Format: PDF
Adder is one among the basic arithmetic operates. Currently, implementing a high speed VLSI style could be an important topic and as adders are utilized in various fields of applications, coming up with a high speed adder is one among the necessary facets. In this paper, the authors designed and enforced a high speed Kogge-stone parallel prefix adder of 8, 16, 32 and 64-bit to be meted out and compared with Carry Look-head Adder (CLA) and Carry Skip Adder (CSA) and also pointed out the potency of Kogge-stone adder with relevance delay victimization using Xilinx ISE 14.7.
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