Design and Implementation of a Modified Canny Edge Detector Based on FPGA

Provided by: IRD India
Topic: Hardware
Format: PDF
In this paper, the authors present a distributed canny edge detection algorithm that results in significantly reduced memory requirements decreased latency and increased throughput with no loss in edge detection performance as compared to the original canny algorithm. The new algorithm uses a low-complexity 8-bin non-uniform gradient magnitude histogram to compute block-based hysteresis thresholds that are used by the canny edge detector. Furthermore, FPGA-based hardware architecture of their proposed algorithm is presented in this paper and the architecture is synthesized on the Xilinx Virtex-4 FPGA.

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