Design and Implementation of an Efficient Modified Booth Multiplier using VHDL
In this paper, the authors present an efficient design of modified booth multiplier and then also implement it. The modified booth recoding method is widely used to generate the partial products for implementation of large parallel multipliers, which adopts the parallel encoding scheme. In this paper, the software design of the modified booth multiplier is explained with the help of flow chart. The simulation is done using Xilinx ISE design suite 14.2 tool and ModelSim tool and the results obtained are shown both for 4 bit and 8 bit multiplication.