Design and Implementation of an FPGA-Based Real-Time Very Low Resolution Face Recognition System

Provided by: International Journals of Advanced Information Science and Technology (IJAIST)
Topic: Security
Format: PDF
Face recognition is a successful application of Image analysis. There are at least some reasons for such trend: VLR (Very Low Resolution) problem. VLR problem happens in many face application systems. Existing algorithms performance is not satisfactory. To overcome the VLR problem, this paper proposes an approach to learn relationship between the high resolution space and the VLR image space for face. Based up on the new approach the face recognition applications under the VLR problem is designed for good visuality. The code will be developed in Verilog using Modelsim and then implemented on Virtex5 FPGA kit. The proposed system provide both highly accurate and extremely fast processing of the image data. Experimental results show that proposed method outperforms existing methods.

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