Design and Implementation of Arbiter Schemes for SDRAM on FPGA
Memories are the storage devices, which typically work with single processing system. Sometimes, multiple systems require accessing the same memory for a number of different processes. This is when the Arbiter comes into picture. Since, a shared memory is one of the fastest techniques for inter-process communication; the design of an arbiter plays a very important role as it acts as a control system for various processes and it also avoids data corruption. With this said, an arbiter is designed and implemented in this paper. It is implemented using VHDL (Verilog Hardware Description Language) in the Xilinx ISE (Integrated Software Environment) Design suite 14.2.