Design and Implementation of Decimation Filter for 15-Bit Sigma-Delta ADC Based on FBGA
A 15-bit sigma-delta ADC for a signal band of 40KHz is designed in Matlab/Simulink and then implemented using Xilinx system generator tool. The second order sigma-delta modulator is designed to work at a signal band of 40KHz at an Over-Sampling Ratio (OSR) of 128 with a sampling frequency of 10.24MHz. The proposed decimation filter design is consists of a third order Cascaded Integrator Comb (CIC) filter followed by two finite impulse response filters. This architecture reduces the need for multiplication which is need very large area.