Design and Implementation of Equiripple FIR Lowpass Filter on FPGA: A Case Study
In this paper, the authors demonstrate the design and implementation of equiripple linear-phase FIR low-pass filter. The filter is modeled using Simulink in Xilinx system generator. The filter co-efficient are generated with the help of FDA tools, and the system generator tool is used for RTL code generation. Further, the model is used as a filter block to interface with ADC-DAC block in VHDL. The design has been prototyped on Spartan-3 DSP prototype board XC3S500FG320 using Integrated Synthesis Environment (ISE) 13.1 tools all in one design suit from Xilinx.