Design and Implementation of FIR Filter Using Low Power Bit-Serial Multiplier
In the paper, the authors propose the implementation of low power FIR filter which is mainly based on bit-serial multiplier. The proposed approach is more efficient compare to conventional FIR filter in terms of power and area. This paper presents 4x4 bit-serial multiplication technique used in signal processing and VLSI design. It's also gives the difference between canonical and transposed forms of FIR filters. Synthesis and simulation of FIR filter is performed using Xilinx ISE 10.1i.