In this paper, the authors propose a VHDL based design of a frequency analyzer that implements a FFT. The module had been developed using radix-2 decimation in time algorithm of n-point samples. Structural and Behavioral modeling was implemented using VHDL to describe, simulate, and perform the design. The resulting design was simulated using Xilinx ISE 9.1i and Modelsim SE 6.3f and can be synthesized on Spartan 3E DSP development board. The simulation results are presented in this paper.